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AR# 4512

Exemplar - Tips for using black box EDIF and XNF netlists in HDL. (CORE Generator)

Description

Keywords: EDIF, XNF, black box, blackbox, instantiate, CORE Generator, COREGen

Urgency: Standard

General Description:
Using Exemplar for Synthesis, I want to instantiate an EDIF or XNF netlist into my HDL code. The netlist is standard Xilinx EDIF/XNF, and may have come from CORE Generator 1.4 (XNF) or 1.5 (EDIF).

Solution

1

EDIF Macro Flow

Assuming you already have a valid EDIF netlist for the macro, you need to instantiate this into your HDL code:

1. Perform a black box instantiation of the EDIF netlist.

2. Proceed to the "Leonardo Flow" or "Galileo Flow" below.

Using CORE Generator 1.5

CORE Generator 1.5 will write out EDIF netlists for the particular module you have created. By default, Exemplar will only write the EDIF netlist using parentheses, so the COREGen EDIF netlist must match this.

1. After starting up COREGen, select the Netlist Bus Format to parenthesis "()".

2. Make the appropriate selections and create the module.

3. Proceed to the "Leonardo Flow" or "Galileo Flow" below.

NOTE: You may have to deselect the HDL instantiation template in order to change the "Netlist Bus Format" (also called the "bus delimiter type) to parenthesis "()". If the HDL instantiation template is needed, you may have to proceed through COREGen twice for a given module.

Leonardo Flow

Process the design as you normally would; however, when you "Write" the EDIF netlist from Leonardo, you must turn off writing of the bus arrays by doing one of the following:

1. In the "Write" dialog box (Menu: IO -> Write, or Flow Guide: Write), click the Advanced button. In the "Set Write Variables" dialog box, DESELECT the following option:

- Allow writing arrays (busses) in EDIF output

Click "Set," then proceed with the EDIF Write as usual.

2. If you are processing the design from the Leonardo command line or from a script file, add the following set command before your write command:

set edif_write_arrays FALSE

Galileo Flow

Process the design as you normally would; however, the bus arrays must not be written in expanded form. There is no checkbox that sets or unsets this option in the Galileo GUI, so the change can be made via the "Special Option" in the GUI, or in a command file:

1. In the Galileo GUI, click on the "Synthesis Options" icon. In the Synthesis Options window, add the following to the "Special Options" field:

-nobus

2. Synthesize the design in Galileo as usual.


Using a Command File:

1. If you do not already have a command file, create one in a text editor. Add the following line to your command file:

-nobus

2. Set this newly created file as your command file. From the main Galileo window, Choose Options -> Control Files from the menu bar; or, in the RUNTIME OPTIONS panel, click "Control Files."

In the "Logic Explorer Control Files" dialog box, set the Command Files field to the file name of the command file from Step 1, then click "OK."

3. Synthesize the design in Galileo as usual.

2

XNF Macro Flow

Assuming you already have a valid EDIF netlist for the macro, you need to instantiate this into your HDL code:

1. Instantiate the XNF netlist as a black box in your HDL code.

2. Proceed to the "Leonardo Flow and Galileo Flow" below.

Using CORE Generator 1.4

CORE Generator 1.5 is the supported product for use with Exemplar. Please upgrade to COREGen 1.5 if you are using COREGen 1.4.x or older.

Use the COREGen-created XNF netlist for the module you create. The XNF Spec will angle bracket "<>" bus delimiters.

1. Make the appropriate choices to create the macro. No special options are needed.

2. Proceed to the "Leonardo Flow and Galileo Flow" below.

Leonardo Flow and Galileo Flow

XNF netlist from Exemplar

This flow is very straightforward. CORE Generator generates an XNF netlist with angle bracket bus delimiters, as does Exemplar. Nothing additional needs to be done. With COREGen v1.4, this is the simplest flow to use.

EDIF netlist from Exemplar

When writing out EDIF from Exemplar, the default bus delimiters will be parenthesis "()". The XNF spec is for bus delimiters to be angle brackets "<>"; because of this, when it passes through the Xilinx core, the tools will produce pin mismatch errors.

In order to resolve the pin mismatches between the bus delimiters, the COREGen XNF must be modified. Using a
text editor, replace all occurrences of angle brackets with parentheses.

Additionally, bus arraying must be disabled as described by the "Leonardo Flow" and "Galileo Flow" sections in the "EDIF Macro Flow" description (Resolution 1).
AR# 4512
Date Created 08/30/1998
Last Updated 04/24/2007
Status Archive
Type General Article