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AR# 45187

Vivado Timing - Timing Delay Names different than TRCE (TWR)


When I run report_timing on my design, the timing delay names (Prop_LUT_A1_O, ...) are different than the traditional trce (twr) timing delay names (Tilo, Tdick, ...).


The timing results from report_timing are based upon new timing delay name associated with the BEL (basic element) instead of COMP (component) based in trce/timing analyzer (twr).

These new timing delay names are more descriptive and easier to understand.

The new timing delay names follow the following format:

1. Timing arc type: Propagation (Prop) delay, Setup (Setup),Hold (Hold), Min Period (Minper)
2. Cell Name: LUT, Carry, fdre, ramb36e1, etc.
3. Source Pin: A1, O1, D, etc.
4. Destination Pin: O, C, etc.

AR# 45187
Date Created 04/30/2012
Last Updated 08/07/2013
Status Active
Type Known Issues
  • Vivado Design Suite - 2012.1
  • Vivado Design Suite - 2012.2
  • Vivado Design Suite - 2012.3
  • More
  • Vivado Design Suite - 2012.4
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
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