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# AR# 45213

## Description

How do I convert STD_LOGIC_VECTOR to Integer in "VHDL - Tips and Tricks"?

## Solution

Type conversion is a regular operation that is performed while writing VHDL code, but it can sometimes be cumbersome to perform properly. An example of this is converting STD_LOGIC_VECTOR types to Integer types. You now have the following options to perform the same:

1. Function "conv_integer" defined in Synopsys Library : std_logic_arith, defined as:

function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
2. Function "To_integer" defined in IEEE library:numeric_std, defined as:

function TO_INTEGER (ARG: UNSIGNED) return INTEGER;
function TO_INTEGER (ARG: SIGNED) return INTEGER;

Of these, numeric_std is an improved package and has more ease of use. Following is example code describinghow to convert a STD_LOGIC_VECTOR to a signed Integer:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

entity conv_test is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : out integer);
end conv_test;

architecture Behavioral of conv_test is

begin

b <= to_integer(signed(a));

end Behavioral;

For unsigned integer, modify the snippet as:

b <= to_integer(unsigned(a));
AR# 45213
Date 02/21/2013
Status Active
Type General Article
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