We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45234

AXI Bridge for PCI Express - 64-bit TLPs are generated when requested address is less than 4GB


Version Found: 1.00.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

The AXI EP Bridge for PCI Express generates 64-bit TLPs when the address lies less than 4GB. This is a violation of the PCI Express Specification defined in section When the requested address lies below the 4GB threshold, TLPs should be 32-bit TLPs.

NOTE: The "Version Found" column lists the version that the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


This is a known issue with the AXI Bridge for PCI Express.

To work around the problem, make sure that you are specifying a range above 4GB by having at least one of the bits set from the C_AXIBAR2PCIEBAR_#U register.

Revision History

12/1/2011 - Initial release
AR# 45234
Date Created 12/01/2011
Last Updated 12/02/2011
Status Active
Type General Article
  • AXI PCI Express (PCIe)