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AR# 45237

LogiCORE IP Triple-Rate SDI (Serial Digital Interface) Virtex-6 - Where do I find the UCF constraints for the SDI reference design?

Description

Where do I find the UCF constraints for the SDI reference design?

Solution

There is no UCF file generated when you generate the SDI IP.This is because the constraints are very simple and fully described in the LogiCORE IP Virtex-6 FPGA Triple-Rate SDI User Guide(UG823).All you have to do is set a period constraint of 148.5 MHz on the RXRECCLK and the TXOUTCLK clocks.

There is also an example UCF file provided with the XAPP1075 demo, that can beused as a guide.

For a detailed list of LogiCORE IP Triple Rate SDI Release Notes and Known Issues, see (Xilinx Answer 40473).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40473 LogiCORE IP Triple-Rate SDI (Serial Digital Interface) Virtex-6 - Release Notes and Known Issues N/A N/A
AR# 45237
Date Created 12/01/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less