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AR# 45241

Logicore SRIO v5.6 - Difficult to meet timing when the transceivers are located at the lower left or the upper left corner


The MODE_4X_SEL belowdrives some nets that go into the transceivers and also nets that go into the BUFGMUX CE pins.

rio_de_wrapper/phy_wrapper_inst/phy_4x_ser/U0/phy_4x_ser_gen.phy_ser/u_oplm_top/u_oplm_pcs_top/u_oplm_pcs_tx_top/u_oplm_pcs_tx_initctl/u_oplm_pcs_tx_initctl_fsm/MODE_4X_SEL (FF)

In the case where Transceivers are used in the middle of the dienear the BUFGMUX, the timing is easier to meet by placing a MODE_4X_SEL Flip-Flop close to the Transceivers. However, if theTransceivers used areat the lowerleft orupper left corner of thedie, the timing becomes difficult to meetas the Flip-Flop will need to be placed in between the Transceivers and the global clock lines, which will cause a large delay on these nets. How can I resolve this issue to make it easier to meet timing in my design where the Transceivers are located at the upper left corner of the die?


To address the above issue, the user can do one of the following:

1. The nets that go into the CE0 and CE1 of the BUFGMUX can be TIGed so that the MODE_4x_SEL flip-flop can be placed closer to the transceivers.

2. The MODE_4X_SEL signal that goes into the CE0 and CE1 of theBUFGMUX can be routed through another register.

Revision History:
12/1/2011 - Initial Release
AR# 45241
Date Created 12/05/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Serial RapidIO