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AR# 45360

Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon

Description

This Design Advisory contains information on attribute settings, issues, and work-arounds for Kintex-7 and Virtex-7 FPGA GTX Transceiver General Engineering Sample (ES) Silicon.

Solution

1. GTX Transceiver Attribute Updates for General Engineering Sample (ES) Silicon

This table shows the GTX attribute updates required for reliable operation of the General ES silicon.

The Initial ES bitstream cannot be used with General ES silicon and vice versa. ISE Design Suite 13.4 generates the following attribute updates natively when using v1.6 of the 7 series FPGA Transceiver Wizard. Version 1.5 of the Wizard only supports the Initial ES Silicon settings and version 1.6 supports only the General ES Silicon settings in ISE 13.4.

The General ES bitstream generated with v2.1 or earlier of the wizard cannot be used with Production silicon and vice versa. When using ISE Design Suite 14.2, 7 series FPGA Transceiver Wizard version 2.2 must be used for the General ES silicon and this bitstream is compatible with GTX production silicon. However, for the latest RXCDR_CFG settings in the table below, v2.3 of the wizard in ISE 14.3/Vivado 2012.3 must be used and this version supports both General ES and production GTX. If using ISE 14.4/Vivado 2012.4, v2.4 must be used and this version supports both General ES and Production GTX silicon. For information on different silicon revisions supported by the wizard versions, please refer to (Xilinx Answer 46048).

 

 

Attribute
Value
BIAS_CFG

64'h0000040000001000

CPLL_CFG 24'hBC07DC
QPLL_CFG

QPLL Lower band: 27'h06801C1

QPLL Upper band: 27'h0680181

QPLL_LOCK_CFG

16'h21E8
QPLL_CP 10'h01F
QPLL_LPF
4'hF

RXCDR_FR_RESET_ON_EIDLE

1'b0

RXCDR_PH_RESET_ON_EIDLE 1'b0
RXCDR_HOLD_DURING_EIDLE
1'b0
RX_DEBUG_CFG 12'h000
RXCDR_CFG Full-rate(1) Half-rate(2) Quarter-rate(3) One-eighth rate(4)
Scrambled and 8B/10B with Pre-scrambling patterns

CDR setting < +/- 200 ppm

LPM mode:

72'h0B_0000_23FF_1040_0020 (> 6.6 Gb/s)

72'h03_0000_23FF_1020_0020 (<= 6.6 Gb/s)

DFE mode:

72'h0B_0000_23FF_1040_0020 (> 6.6 Gb/s)

72'h03_0000_23FF_2040_0020 (<= 6.6 Gb/s)

 

CDR setting < +/- 700 ppm

LPM mode:

72'h0B_8000_23FF_1040_0020 (> 6.6 Gb/s)

72'h03_8000_23FF_1020_0020 (<= 6.6 Gb/s)

DFE mode:

72'h0B_8000_23FF_1040_0020 (> 6.6 Gb/s)

72'h03_8000_23FF_2040_0020 (<= 6.6 Gb/s)

CDR setting < +/- 1250 ppm

 

LPM mode:

 

72'h0B_8000_23FF_1020_0020 (> 6.6 Gb/s)

72'h03_8000_23FF_1020_0020 (<= 6.6 Gb/s)

 

DFE mode:

 

72'h0B_8000_23FF_1020_0020 (> 6.6 Gb/s)

72'h03_8000_23FF_1020_0020 (<= 6.6 Gb/s)

 

CDR setting < +/- 200 ppm

LPM/DFE mode:

72'h03_0000_23FF_4020_0020

 

CDR setting < +/- 700 ppm

LPM/DFE mode:

72'h03_8000_23FF_4020_0020

 

CDR setting < +/- 1250 ppm

LPM/DFE mode:

72'h03_8000_23FF_4020_0020

 

CDR setting < +/- 200 ppm

LPM/DFE mode:

72'h03_0000_23FF_4010_0020

 

CDR setting < +/- 700 ppm

LPM/DFE mode:

72'h03_8000_23FF_4010_0020

 

CDR setting < +/- 1250 ppm

LPM/DFE mode:

72'h03_8000_23FF_4010_0020

CDR setting < +/- 200 ppm

LPM/DFE mode:

72'h03_0000_23FF_4008_0020

 

CDR setting < +/- 700 ppm

LPM/DFE mode:

72'h03_8000_23FF_4008_0020

 

CDR setting < +/- 1250 ppm

LPM/DFE mode:

72'h03_8000_23FF_4008_0020

8B/10B without Pre-scramble pattern

CDR setting < +/- 200 ppm

LPM mode:

72'h03_0000_23FF_1040_0020

 

CDR setting < +/- 700 ppm

LPM mode:

72'h03_8000_23FF_1040_0020

 

CDR setting < +/- 1250 ppm

LPM mode:

72'h03_8000_23FF_1040_0020

CDR setting < +/- 200 ppm

LPM mode:

72'h03_0000_23FF_1020_0020

 

CDR setting < +/- 700 ppm

LPM mode:

72'h03_8000_23FF_1020_0020

 

CDR setting < +/- 1250 ppm

LPM mode:

72'h03_8000_23FF_1020_0020

CDR setting < +/- 200 ppm

LPM mode:

72'h03_0000_23FF_1010_0020

 

CDR setting < +/- 700 ppm

LPM mode:

72'h03_8000_23FF_1010_0020

CDR setting < +/- 1250 ppm

LPM mode:

72'h03_8000_23FF_1010_0020

CDR setting < +/- 200 ppm

LPM mode:

72'h03_0000_23FF_1008_0020

CDR setting < +/- 700 ppm

LPM mode:

72'h03_8000_23FF_1008_0020

CDR setting < +/- 1250 ppm

LPM mode:

72'h03_8000_23FF_1008_0020

SATA REFCLK PPM with SSC setting(5) 72'h03_8000_8BFF_1020_0010 (Gen 3 at 6 Gb/s) 72'h03_8800_8BFF_4020_0008 (Gen 2 at 3 Gb/s) 72'h03_8000_8BFF_4010_0008 (Gen 1 at 1.5 Gb/s)
RXCDR_LOCK_CFG

6'b010101(6)

RX_BIAS_CFG

12'b000000000100

RX_OS_CFG
13'b0000010000000
RX_DFE_LPM_HOLD_DURING_EIDLE 1'b0
PMA_RSV

32'h 0001_8480(7)

32'h 001E_7080(8)

PMA_RSV2[5]

1'b1 (9)

1'b0 (10)

ES_EYE_SCAN_EN TRUE
RX_CM_SEL 2'b11
PMA_RSV2[4], RX_CM_TRIM 1'b1, 3'b010 (11)
PCS_RSVD_ATTR[8]

1'b1(12)

1'b0(13)

RX_DFE_XYD_CFG 13'h0000
DFE mode Internal Serial Loopback Channel
RX_DFE_GAIN_CFG 23'h0207EA 23'h020FEA
RX_DFE_VP_CFG 17'b00011111100000011 17'b00011111100000011
RX_DFE_UT_CFG 17'b10001000000000000 17'b10001111000000000
RX_DFE_KL_CFG 13'b0000011111110 13'b0000011111110
RX_DFE_KL_CFG2 32'h3788140A As per user guide (UG476) use models(14)
RX_DFE_H2_CFG 12'b000110000000 12'b000000000000
RX_DFE_H3_CFG

12'b000110000000

12'b000001000000
RX_DFE_H4_CFG 11'b00011100000 11'b00011110000
RX_DFE_H5_CFG 11'b00011100000 11'b00011100000
RX_DFE_LPM_CFG 16'h0954 16'h0954
LPM mode Short channel (<=2.5 dB loss) Long channel (>2.5 dB loss)
RXLPM_HF_CFG 14'b00000000000000 14'b00000011110000
RXLPM_LF_CFG 14'b00000000000000 14'b00000011110000
RX_DFE_LPM_CFG

16'h0904(15)

16'h0104(16)

16'h0904(15)

16'h0104(16)

Notes:

  1. CPLL/QPLL Full-rate setting: For QPLL operation in 5.93 to 8.0 Gb/s and 9.8 to 10.3125 Gb/s line rate, and CPLL operation in 3.2 to 6.6 Gb/s line rate with divider of 1.
  2. CPLL/QPLL Half-rate setting: For QPLL operation in 2.965 to 4.0 Gb/s and 4.9 to 5.15625 Gb/s line rate, and CPLL operation in 1.6 to 3.3 Gb/s line rate with divider of 2.
  3. CPLL/QPLL Quarter-rate setting: For QPLL operation in 1.4825 to 2.0 Gb/s and 2.45 to 2.578125 Gb/s line rate, and CPLL operation in 0.8 to 1.65 Gb/s line rate with divider of 4.
  4. CPLL/QPLL One-eighth rate setting: For QPLL operation in 0.74125 to 1.0 Gb/s and 1.225 to 1.2890625 Gb/s line rate, and CPLL operation in 0.4 to 0.825 Gb/s line rate with divider of 8.
  5. This setting is to support SATA requirement for REFCLK PPM with SSC: +/- 700PPM with 33KHz FM Triangular modulation of -5000PPM. 
  6. The RXCDRLOCK port is not supported. It is recommended to verify the incoming data.
  7. Lower Line Rates: CPLL full range, 5.93 GHz <= QPLL VCO frequency <= 6.6 GHz
  8. Higher Line Rates: QPLL VCO frequency > 6.6 GHz
  9. When using the eye scan feature, ES_EYE_SCAN_EN and PMA_RSV2[5] must be set to 1'b1.
  10. When not using eye scan, ES_EYE_SCAN_EN must be set to 1'b1, and PMA_RSV2[5] must be set to 1'b0.
  11. Programmable, set to 800 mV. Applies when RX_CM_SEL = 2'b11. In LPM mode, PMA_RSV2[4] and RX_CM_TRIM are don't care when RX_CM_SEL = 2'b00.
  12. For designs using OOB (PCI Express, SATA/SAS etc.), PCS_RSVD_ATTR[8] must be set to 1'b1.
  13. For designs not using OOB, PCS_RSVD_ATTR[8] must be set to 1'b0; RXELECIDLEMODE[1:0] must be set to 2'b11 and RXBUF_RESET_ON_EIDLE must be set to FALSE.
  14. RX_DFE_KL_CFG2 should be set based on channel insertion loss - refer to UG476 tables 4-12 and 4-13. Transceiver wizard v2.6 and later sets this to 32'h301148AC assuming worst-case channel insertion loss of 25 - 30 dB at Nyquist frequency. 
  15. For line rates <= 6.6 Gb/s.
  16. For line rates > 6.6 Gb/s.

 

2. General ES Silicon GTX Errata Items

This section refers to the Kintex-7 FPGA CES errata for General ES silicon.

  1. CPLL Power Down

The GTX transceiver CPLL can become inoperative if conditions (a) and (b) persist for greater than 8,000 hours:

  1. Power has been applied to MGTAVCC and MGTAVTT.
  2. The device is in one of the following states:
    1. The FPGA is not configured.
    2. The FPGA is configured, but the transceiver is un-instantiated.
    3. The transceiver is instantiated, but the CPLL is held in powerdown state.

When the QPLL is being used, enabling each CPLL will consume up to 30 mA on the MGTAVTT supply and 20 mA on MGTAVCC.

This requires that the CPLL always be powered on even when only the QPLL is used by setting the CPLL powerdown port CPLLPD always to 1'b0.

3. Use Modes

Eye Scan Use mode

ES_EYE_SCAN_EN PMA_RSV2[5] Description
TRUE 1'b0 Eye Scan disabled
TRUE 1'b1 Eye Scan enabled


OOB Use Mode

PCS_RSVD_ATTR[8] Description
1'b0 OOB powered down
1'b1 OOB powered on

NOTE: OOB circuitry must be powered on for applications such as PCI Express, SATA/SAS.

4. GTX Software Known Issues/Use Mode Changes

For the latest GTX software use mode changes and known issues, please refer to (Xilinx Answer 43339).

5. Initial ES to General ES Migration for GTX

For customers looking at migrating designs using GTX from Initial ES to General ES silicon, there are several things to consider as discussed in (Xilinx Answer 45410).

Revision History
05/05/2014 - Updated the RXCDR_CFG setting for SATA Gen 2/Gen 3 and PMA_RSV for 6.6 Gbps
11/22/2013 - Updated the table to refer to the user guide UG476 for RX_DFE_KL_CFG2 setting since it is channel dependent.
12/12/2012 - Added the RXCDR_CFG setting for SATA SSC and added a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.
10/18/2012 - Added/updated RXCDR_CFG settings for scrambled/non-scrambled 8B/10B and non-8B/10B patterns.
07/19/2012 - Added the RX_DFE_XYD_CFG value to the attributes table.
06/28/2012 - Updated GTX software use mode changes (Xilinx Answer 43339) with the latest GTXE2_COMMON use model change information.
03/22/2012 - Updated RXCDR_CFG settings for half-rate mode.
02/22/2012 - Added RXCDR_CFG settings for quarter-rate and one-eighth rate. Added a link to GTX software known issues/use mode changes.
01/12/2012 - Initial release

Linked Answer Records

Associated Answer Records

AR# 45360
Date Created 01/12/2012
Last Updated 05/23/2014
Status Active
Type Design Advisory
Devices
  • Virtex-7
  • Kintex-7