To begin debugging a suspected hardware issue on the VC707, please see (Xilinx Answer 51233) Virtex-7 FPGA VC707 Evaluation Kit - Board Debug Checklist.
The VC707 Board Debug Checklist forms part of(Xilinx Answer 43745)Xilinx Boards and Kits Solution Center.

Board/Kit Related Issues
(Xilinx Answer 37579) What device do I have on my Xilinx Evaluation Kit? Is it Engineering Sample (ES) or Production Silicon?
(Xilinx Answer 47347) Virtex-7 FPGA VC707 Evaluation Kit - MGTVCCAUX Voltage Clarification
(Xilinx Answer 45380) Development Boards - Xilinx PCIe form factor board TI power system cooling
(Xilinx Answer 43514) Development Boards - Device on board does not match schematic
(Xilinx Answer 50596) Xilinx Evaluation Kits, PCIe cards - CE requirements for PC test environment
(Xilinx Answer 50804) VC707 - HB bus signals on the FMC2 header
(Xilinx Answer 53870)Virtex-7 FPGA VC707 Evaluation Kit - USB drive no longer provided in the box

Documentation Related Issues
(Xilinx Answer 46903) Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.0) states incorrect SGMII clock frequency
(Xilinx Answer 50110) Virtex-7 FPGA VC707 - Master UCF (Rev 1.0) I/O Standard for USER_CLOCK Differential Pair
(Xilinx Answer 51139) VC707 UG885 (v1.0) - FPGA to LCD Header Connections
(Xilinx Answer 52084) VC707 Evaluation Board for the Virtex-7 FPGA User Guide (UG885) - SFP+ Module Connections
(Xilinx Answer 52944) UG885 (v1.1) - VC707 Evaluation Board for the Virtex-7 FPGA User Guide - HA pairs listed twice for FMC connectors
(Xilinx Answer 54085) Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.1) - Table 1-26 Directional Pushbutton Switches
(Xilinx Answer 54086) Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.1) - Table 1-11 GTX Interface Connections are incorrect
(Xilinx Answer 54209) Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.2) - EMCCLK settings for Linear BPI Flash Memory configuration incorrect

PCI Express/IP Related Issues
(Xilinx Answer 40469) 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions

Design Tools Related Issues
(Xilinx Answer 40905) 7 Series - ISE 13.x Software Known Issues related to the 7 Series FPGAs
(Xilinx Answer 44191) 13.3 Kintex-7/Virtex-7, ChipScope IBERT - Using the KC705 or VC707 Board Configuration Settings file causes implementation error
(Xilinx Answer 45648) 13.1, 13.2, 13.3, 13.4, Virtex-7/Kintex-7 - Using KC705 or VC707 "Board Configuration Setting" in GTX IBERT uses incorrect I/O Standard for system clock
(Xilinx Answer 46253) ChipScope IBERT, Virtex-6, Kintex-7, Virtex-7 - 12 MHz cable speed does not work with IBERT
(Xilinx Answer 47816) 7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGAs
(Xilinx Answer 50886) 14.2 Speed Files - Tactical Patch for 7 Series GES devices
(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices
(Xilinx Answer 52368) 14.3/2012.3 Speed Files - Tactical Patch for 7 Series GES -2 Devices