This error can occur when neither VHDL nor Verilog outputs are chosen in the project options.This state should only be possible if a user has edited the ".xco" file outside of the CORE Generator tool.
The use case of selecting neither VHDL nor Verilog is very rare; it isonly available by editing the".xco" files.
Before generating the core, verify that either thevhdlsim or verilogsim property is set to "true".