To work around this issue, make thefollowing changesin the*_block.vhd (v) file:
Verilog:
From:
mgt_rxlock_r1 <= mgt_rxlock and (not mgt_rxelecidle_i) ;
To:
mgt_rxlock_r1 <= {4{mgt_plllocked}};
VHDL:
From:
mgt_rxlock_r1 <= mgt_rxlock and (not mgt_rxelecidle_i) ;
To:
mgt_rxlock_r1 <= (mgt_plllocked & mgt_plllocked & mgt_plllocked & mgt_plllocked);
Revision History
03/06/2012 - Fixed typo
02/27/2012 - Updated to include General ES devices
01/26/2012 - Updated to include Virtex-7 Initial ES deviceand XAUI v10.2
12/17/2011 - Initial Release