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AR# 45516

System Generator for DSP - System Generator GUI reports incorrect latency value of Divider Generator (AXI) v4.0. Is there a workaround?


The Divider Generator block in the System Generator model reports a latency of 21 for the particular core settings. However, all simulations (both in Simulink and ISim) and the CORE Generator indicate that the core should have 30 cycles of latency for the same settings.Is there a workaround?


There is an issue with the DivGen 4.0 block Latency field. The workaround is to run simulation to determine the correct latency value.

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
29595 Xilinx DSP Tools, System Generator for DSP, and AccelDSP Synthesis Tool - Release Notes and Known Issues N/A N/A
AR# 45516
Date Created 01/16/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
  • System Generator for DSP - 13.3
  • System Generator for DSP - 13.4