Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).
When targeting a -2L speedgrade a pin to pin timing constraint failure is reported.
Timing constraint: Pin to Pin Skew Constraint;
2 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
2 timing errors detected.
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Slack: -0.019ns (maxskew - uncertainty - (arrival1 - arrival2))
Max skew: 0.510ns
Arrival 1: 4.810ns core_i/pcie_top_i/pcie_7x_i/core_i/pcie_top_i/pcie_7x_i/pcie_block_i/PIPECLK
Arrival 2: 4.316ns core_i/pcie_top_i/pcie_7x_i/core_i/pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK
Clock Uncertainty: 0.035ns
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Slack: -0.019ns (maxskew - uncertainty - (arrival1 - arrival2))
Max skew: 0.510ns
Arrival 1: 4.810ns core_i/pcie_top_i/pcie_7x_i/core_i/pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK2
Arrival 2: 4.316ns core_i/pcie_top_i/pcie_7x_i/core_i/pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK
Clock Uncertainty: 0.035ns
Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
This issue is fixed in ISE 13.4 software.
Revision History
12/20/2011 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 40469 | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions | N/A | N/A |