Is there any restriction on the address of the memory controller interface (MCI) and PLB?
Any PLB peripherals can be in the same 128MByte MCI address range.
The address for MCI can be specified by the address template registers (TMPLx_XBAR_MAP).
It divides the 4 GB address space into 128 MB regions.
If the bit corresponding to a 128 MB region is set, that request is forwarded to the MCI.
Otherwise, it is sent to the MPLB.