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AR# 45644

MIG 7 Series DDR2/DDR3 - Memory Controller Latency

Description

The overallreadlatency of the MIG 7 Series DDR3/DDR2 coreis dependent on how the memory controlleris configured,butmost critically on the target traffic/access pattern.Read latency is measured from the point where the read command is accepted by the UI or native interface. In general, read latency varies based on several parameters:
- The number of commands already in the pipeline before the read command is issued
- Whether an ACTIVATE command needs to be issued to open the new bank/row
- Whether a PRECHARGE command needs to be issued to close a previously opened Bank
- Specific timing parameters for the memory, such as TRAS and TRCD in conjunction with the bus clock frequency
- Commands can be interrupted, and banks/rows can forcibly be closed when the periodic AUTO REFRESH command is issued
- CAS latency

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Simulation should be used to calculate the latency with the target traffic pattern. Latency to an open and un-opened bank will vary slightly.

General read latency can be measured withrefresh, zqcalib, and periodic reads disabled. Worst case read latency should have these items included.

Additional Information
The additionalnumber of fabric clock cycles required for switching from a read to write command can sometimes be affected by all the Bank Machines used. Increasing the number of Bank Machines can sometimes improve efficiency and turnaround times. For more information on the design's usage of Bank Machines and how to change the number of Bank Machines, please see (Xilinx Answer 36505).
For higher frequency designs, a 4:1 memory to FPGA logic interface clock ratio is used which means for every fabric clock cyclefour DRAM clock cycles will occur. Using 2:1 mode at slower frequencies can sometimes reduce the turnaround latency by reducing the number of DRAM clock cycles that occur for every fabric clock cycle.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51705 MIG 7 Series Solution Center - Design Assistant - Performance N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36505 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Bank Machines N/A N/A
AR# 45644
Date Created 01/06/2012
Last Updated 02/08/2013
Status Active
Type Solution Center
Devices
  • Virtex-7
  • Artix-7
  • Kintex-7
IP
  • MIG 7 Series