The OCLK_DELAY calibration requires reads to be correct, therefore, since the OCLK_DELAY calibration occurs before the Read Leveling stage of calibration, a Multi Purpose Register (MPR) read leveling calibration is performed for correct read functionality before the OCLK_DELAY calibration begins. During OCLK_DELAY calibration, the algorithm performs the following:
- Decrements the OCLK_DELAY taps from 30 until either a DQ edge is detected or a tap value of 0.
- Increments the OCLK_DELAY taps back to 30 and begins DQ edge detection with every increment past 30 taps.
- Then, places DQS in the center of the two detected edges.
- Then, uses a pattern calibration for all subsequent stages so it can differentiate between early, on time, and late reads and writes.
Without the OCLK_DELAY calibration stage added it is possible the Phase between DQS and DQ during writes could be out of specification and cause calibration failures. In addition to the new OCLK_DELAY calibration stage, since the MIG 7 Series v1.4 release, an additional update to the OCLK_DELAY is required for all users working in hardware. For this reason, Xilinx recommends upgrading to MIG 7 Series v1.4 and installing the patch provided in
(Xilinx Answer 45653).
The OCLK_DELAY calibration is also planned to be added for QDRII+ and RLDRAMII designs starting in software version 14.1. For more details, refer to
(Xilinx Answer 45447).