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AR# 45648 Virtex-7, Kintex-7 - Using KC705 or VC707 "Board Configuration Setting" in GTX IBERT uses an incorrect I/O Standard for the system clock

Description

When I use one of the KC705 or VC707 "Board Configuration Settings" in the GTX IBERT core (Kintex-7 or Virtex-7 devices), an incorrect I/O Standard is selected for the system clock.

Solution

This issue only affects users who use IBERT under the following conditions:

  • Using ChipScope tool versions 13.1, 13.2, 13.3, 13.4, or 14.1
  • Targeting a KC705 or VC707 development board
  • Using one of the KC705 or VC707 "Board Configuration Settings" when generating the GTX IBERT core

The 200 MHz oscillator that is on the KC705 and VC707 development boards uses a LVDS_25 I/O Standard. The KC705 and VC707 Board Configuration Setting automatically selects a DIFF_SSTL standard, which is incorrect.

To work around the issue, manually select the LVDS_25 setting for the system clock instead of DIFF_SSTL to ensure proper operation of the IBERT design.

This issue is scheduled to be fixed in ChipScope tool version 14.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47769 14.x ChipScope Pro and 2012.x Vivado Debug - Known Issues for the 14.x ChipScope Pro and 2012.x Vivado Debug tools N/A N/A
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Actions

AR# 45648
Date Created 01/04/2012
Last Updated 07/17/2012
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
Tools
  • ChipScope Pro - 13.1
  • ChipScope Pro - 13.2
  • ChipScope Pro - 13.3
  • More
  • ChipScope Pro - 13.4
  • ChipScope Pro - 14.1
  • Less
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit
  • Virtex-7 FPGA VC707 Evaluation Kit
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