UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45666

MIG 7 Series v1.4 DDR3 - Generate unrouted design for multi-controller design

Description

In MIG v1.3-v1.4, for multi-controller designs, during bank selection, it is possible to allocate multiple system clock pins to different CC_P/N pins in the same bank.

If this same bank also has byte groups allocated to it for either of the memory controllers, an unroutable situation will occur.

Solution

This configuration will not route completely because of the limited number of CMT Backbone routes available. 

The CMT BackBone has four routes available (see UG472 Figure 1-2) while this configuration requires five for the following signals:

  • c0_sys_clk_p/n
  • c0_freq_refclk
  • c0_mem_refclk
  • c0_sync_pulse
  • c1_sys_clk_p/n
 
During implementation, the following warning will occur which will cause PAR to fail:

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:



To work around the problem you must allocate one of the system clock pins to a CC_P/N pair in a different bank.

This is an illegal configuration that MIG should not allow and will be fixed in MIG v1.6.
AR# 45666
Date Created 01/06/2012
Last Updated 08/19/2014
Status Active
Type Known Issues
Devices
  • Virtex-7
  • Kintex-7
IP
  • MIG 7 Series