In Project Navigator, there are several different types of simulation available. The simulation types are selected by navigating to theSimulation tab and selecting the appropriate type from the drop-down menu. The options available are as follows:
- Post - Translate
- Post - MAP
- Post - Place and Route (Timing)
If you want to run a Post - Synthesis simulation, you will not be able to perform it by the GUI options.
Follow these steps to run simulation:
- Create the project in ISE Project Navigator and add all the required modules including the testbench.
- Set the module (DUT)you want to perform Post-Synthesis Simulation as the Top Module.
- Run Synthesis.
- Once the design is synthesized. Expand the Synthesize -> XST option and double-click on Generate Post-Synthesis Simulation Model. This runs NetGen to create the simulation netlist. The output is placed inthe "./netgen/synthesis" folderin your project directory. The file generatedis named: <top_module_name>_synthesis.vhd/v. This file would be a VHDL or Verilog file depending on the source file of the synthesized module. Alternately, you can right-click onGenerate Post-Synthesis Simulation Model and change the value of Simulation Model Target (VHDL/Verilog) as per your needs.
- In your "project" directory, create a new ".prj" file. Add the two entries as shown below:
vhdl/verilog work (or library name)"netgen\synthesis\<top_module_name>_synthesis.vhd/v"
vhdl/verilog work (or library name) "testbench.vhd/v"
- Open the ISE Design Suite Command Prompt and run the following commands (depending on simulation language):
- Verilog: fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench>work.glbl
- VHDL: fuse -intstyle ise -incremental -lib unisim -lib unimacro -lib xilinxcorelib -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench>
- Run the generated simulation executable x_synthesis.exe -gui to open ISIM GUI.
- The outputted waveform is the Post-Synthesis Simulation for the design under test.