UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45674

13.4 and earlier - Virtex-7 and Kintex-7 - GTX IBERT core with 562.5 MHz refclk may cause map error

Description

If the Virtex-7 or Kintex-7 GTX IBERT core is used under the following conditions, an implementation errorwill occur during MAP:

  • Running ISE 13.4 software and earlier
  • Using the Kintex-7 or Virtex-7 GTX IBERT core
  • Reference clock = 562.5 MHz

The following error message will occur in Map if the above conditions are met:

ERROR:PhysDesignRules:2042 - The DIVCLK_DIVIDE value 1.000000 of MMCME2_ADV instance
U_CHIPSCOPE_IBERT/U0/U_IBERT_CORE/U_USRCLK_DIVIDER_2/mmcm_adv_inst is below the Fin / Fpfd value 1.125000, where Fin
is the input frequency, 562.499930 MHz, and Fpfd min - max values of 10.000000 - 500.000000 MHz.

Solution

This issue is caused by a bug in the algorithm which determines appropriate M and D values for the MMCM used with the IBERT core to generate the USRCLKs for the GTs. For this frequency, the M and D values are set to an illegal value. At this time, a reference clock of 562.5 MHz cannot be used with the 7 series GTX IBERT core. This issue will be fixed in ISE 14.1 software.
AR# 45674
Date Created 01/13/2012
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
Tools
  • ChipScope Pro - 13.1
  • ChipScope Pro - 13.2
  • ChipScope Pro - 13.3
  • ChipScope Pro - 13.4