Functional simulation failures are seen for the Ethernet 1000BASE-X PCS/PMA or SGMII version 11.2 core when the STANDARD parameter is set to 1000BASEX and using VHDL design entry and simulation. The failures seen are:
Running functional simulation in Modelsim
Fatal: (vsim-3471) Slice range (11 downto 0) does not belong to the prefix index range (10 downto 0).
FATAL ERROR while loading design
Running functional simulation in IUS
ncelab: *E,TRINDXC: index constraint violation.
source file: GTXE2_CHANNEL.vhd, line = 1028, position = 99
To resolve this issue, on line 300 of <core_name>/example_design/transceiver/gtwizard_gt.vhd change the following:
From:
RX_BIAS_CFG => ("00000000010"),
To:
RX_BIAS_CFG => ("000000000100"),