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AR# 45679

Kintex-7 FPGA Base Targeted Reference Design - Release Notes and Known Issues Master Answer Record

Description

This answer record contains the Release Notes and Known Issues for the Kintex-7 FPGA Base Targeted Reference Design (TRD). 

The purpose of this answer record is to help the user avoid running into issues when performing intended operations with the Base TRD.

Solution

The Kintex-7 FPGA Base TRD is developed on the Kintex-7 FPGA KC705 Evaluation Kit.

The primary components of the TRD are:

  • Integrated Endpoint block for PCI Express
  • Northwest Logic Packet DMA
  • Multiport Virtual FIFO built using MIG, AXI Interconnect and FIFO Generator IP cores

Hardware Test Setup Requirements

(Xilinx Answer 55926) - Kintex-7 FPGA KC705 Evaluation Kit - Recommended machines for Kintex-7 FPGA Base Targeted Reference Design

The prerequisites required to run and test the Base TRD are:

  • KC705 Evaluation kit with the XC7K325T-2FFG900C FPGA
  • Design files provided on a USB memory stick as a zipped collection including:
    • Design source files
    • Device driver files
    • Board design files
    • Documentation
  • ISE Design Suite, Logic Edition v13.4 or later
  • Micro USB cable
  • PCIe adapter cable, 4-Pin to 6-Pin
  • Fedora 16 Live DVD for Intel-compatible PCs or pre-installed Fedora 16 Linux OS
  • PC with PCIe v2.0 slot.

Simulation Requirements

The tools required to simulate the Base TRD are:

  • ISE Design Suite, Logic Edition v13.4 or later
  • ModelSim simulation software, v6.6d or later

 

K7 Base
TRD

 

Silicon ISE Vivado PCIe
NWL Packet DMA

 

Memory
Controller (MIG)

 

AXI
Interconnect

FIFO
Generator

v1.0 GES 13.4 v1.3 v1.07 v1.4 v1.05.a v8.4
v1.1 GES 14.1 v1.4 v1.08 v1.5 v1.06.a v9.1
v1.2 GES 14.2 2012.2 v1.6 v1.08 v1.6 v1.06.a v9.2
v1.3 GES 14.3 2012.3 v1.7 v1.08 v1.7 v1.06.a v9.3
v1.4 GES 14.4 2012.4 v1.8 v1.08 v1.8 v1.06.a v9.3
v1.5 C 2013.1 v2.0 v1.08 v1.8.a v1.06.a v9.3
v1.6 C 2014.2 v3.0 v1.08 v2.1 v1.7 v12.0
v1.7 C 2014.3 v3.0 v1.08 v2.2 v1.7 v12.0


Kintex-7 Base TRD v1.0 for ISE 13.4 with GES Silicon

  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with GES silicon. Refer to GES Errata for any further information.
  • IP Cores
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16 Linux. Windows driver support is not available
    • When implementing the design in the PlanAhead flow, 50 Critical warnings are reported with regards to clock period (REFCLK_PERIOD, MEMREFCLK_PERIOD, PHASEREFCLK_PERIOD). Ignore these warnings.
      The issue will be fixed in the next version of the ISE design tools.
    • If design files are changed, there is a possibility that timing will not be met. Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value. Use the tag option of implement.sh to make output directories unique.
      Every effort has been made to have the default cost table meet timing, however due to varying conditions the default cost table cannot be guaranteed to meet timing.

Kintex-7 Base TRD v1.1 for ISE 14.1 with GES Silicon

  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with GES silicon. Refer to GES Errata for any further information.
  • IP Cores
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16 Linux. Windows driver support is not available.
    • If design files are changed, there is a possibility that timing will not be met. Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value. Use the tag option of implement.sh to make output directories unique.
      Every effort has been made to have the default cost table meet timing. However, due to varying conditions, the default cost table cannot be guaranteed to meet timing.
Kintex-7 Base TRD v1.2 for ISE 14.2 and Vivado 2012.2 with GES Silicon
  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with GES silicon. Refer to GES Errata for any further information.
  • IP Cores
    • Memory Controller (MIG): The TRD uses custom MIG Files (Xilinx Answer 45680)
    • IPs delivered from Xilinx IP Catalog (Vivado Flow): only xci or xc files are included
    • When generating the MIG core in Core Generator or IP Catalog, validating the pinout may cause warnings about slew rate values. These warnings can be safely ignored
    • 7 Series Integrated Block for PCI Express v1.6 - The core does not link up on Z77 (Ivy Bridge) platform (Xilinx Answer 51135)
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16.2 Linux. Windows driver support is not available.
    • If design files are changed, there is a possibility that timing will not be met. Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value. Use the tag option of implement.sh to make output directories unique. Every effort has been made to have the default cost table meet timing, however due to varying conditions the default cost table cannot be guaranteed to meet timing
    • Bitstream compatibility between General ES and Production devices with design tools version 14.2 / 2012.2 (Xilinx Answer 50906)
    • Speed file patch for General ES devices when using design tools 14.2 / 2012.2 (Xilinx Answer 50886)
Kintex-7 Base TRD v1.3 for ISE 14.3 and Vivado 2012.3 with GES Silicon
  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with GES silicon. Refer to GES Errata for any further information.
  • IP Cores
    • Memory Controller (MIG): The TRD uses custom MIG Files (Xilinx Answer 45680)
    • IPs delivered from Xilinx IP Catalog (Vivado Flow): only xci or xc files are included.
    • When generating the MIG core in Core Generator or IP Catalog, validating the pinout may cause warnings about slew rate values. These warnings can be safely ignored.
    • 7 Series Integrated Block for PCI Express v1.6 - The core does not link up on Z77 (Ivy Bridge) platform (Xilinx Answer 51135)

  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16.2 Linux. Windows driver support is not available.
    • If design files are changed, there is a possibility that timing will not be met. Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value. Use the tag option of implement.sh to make output directories unique.
      Every effort has been made to have the default cost table meet timing, however due to varying conditions the default cost table cannot be guaranteed to meet timing
    • Bitstream compatibility between General ES and Production devices with design tools version 14.2 / 2012.2 (Xilinx Answer 50906)
    • Speed file patch for General ES devices when using design tools 14.3 / 2012.3 (Xilinx Answer 52368)
Kintex-7 Base TRD v11.4 for ISE 14.4 and Vivado 2012.4 with GES Silicon
  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with GES silicon. Refer to GES Errata for any further information.
  • IP Cores
    • Memory Controller (MIG): The TRD uses custom MIG Files (Xilinx Answer 45680)
    • IPs delivered from Xilinx IP Catalog (Vivado Flow): only xci or xc files are included.
    • When generating the MIG core in Core Generator or IP Catalog, validating the pinout may cause warnings about slew rate values. These warnings can be safely ignored.
    • 7 Series Integrated Block for PCI Express v1.6 - The core does not link up on Z77 (Ivy Bridge) platform (Xilinx Answer 51135)

  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16.2 Linux. Windows driver support is not available.
    • If design files are changed, there is a possibility that timing will not be met. Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value. Use the tag option of implement.sh to make output directories unique.
      Every effort has been made to have the default cost table meet timing, however due to varying conditions the default cost table cannot be guaranteed to meet timing
    • Bitstream compatibility between General ES and Production devices with design tools version 14.2 / 2012.2 (Xilinx Answer 50906)
    • Speed file patch for General ES devices when using design tools 14.4 / 2012.4 (Xilinx Answer 53392)

 

Kintex-7 Base TRD v1.5 for Vivado 2013.1
  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD uses custom MIG Files (Xilinx Answer 45680)
    • IPs delivered from Xilinx IP Catalog (Vivado Flow): only xci or xc files are included.
    • When generating the MIG core in Core Generator or IP Catalog, validating the pinout may cause warnings about slew rate values. These warnings can be safely ignored.
    • 7 Series Integrated Block for PCI Express v1.6 - The core does not link up on Z77 (Ivy Bridge) platform (Xilinx Answer 51135)

  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16.2 Linux. Windows driver support is not available.
    • If design files are changed, there is a possibility that timing will not be met. Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value. Use the tag option of implement.sh to make output directories unique.
      Every effort has been made to have the default cost table meet timing, however due to varying conditions the default cost table cannot be guaranteed to meet timing
    • Bitstream compatibility between General ES and Production devices with design tools version 14.2 / 2012.2 (Xilinx Answer 50906)
    • Speed file patch for General ES devices when using design tools 2013.1 (Xilinx Answer 55661)

Kintex-7 Base TRD v1.6 for Vivado 2014.2
  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD uses custom MIG Files (Xilinx Answer 45680)
    • IPs delivered from Xilinx IP Catalog (Vivado Flow): only xci or xc files are included.
    • When generating the MIG core in Core Generator or IP Catalog, validating the pinout may cause warnings about slew rate values. These warnings can be safely ignored.
    • 7 Series Integrated Block for PCI Express v1.6 - The core does not link up on Z77 (Ivy Bridge) platform (Xilinx Answer 51135)

  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16.2 Linux. Windows driver support is not available.
    • If design files are changed, there is a possibility that timing will not be met. Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value. Use the tag option of implement.sh to make output directories unique.
      Every effort has been made to have the default cost table meet timing, however due to varying conditions the default cost table cannot be guaranteed to meet timing.
    • Bitstream compatibility between General ES and Production devices with design tools version 14.2 / 2012.2 (Xilinx Answer 50906)
    • Speed file patch for General ES devices when using design tools 2013.1 (Xilinx Answer 55661)

Kintex-7 Base TRD v1.7 for Vivado 2014.3
  • Silicon
    • The Kintex-7 FPGA KC705 Evaluation Kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD uses custom MIG Files (Xilinx Answer 45680)
    • IPs delivered from Xilinx IP Catalog (Vivado Flow): only xci or xc files are included.
    • When generating the MIG core in Core Generator or IP Catalog, validating the pinout may cause warnings about slew rate values. These warnings can be safely ignored.
    • 7 Series Integrated Block for PCI Express v1.6 - The core does not link up on Z77 (Ivy Bridge) platform (Xilinx Answer 51135)

  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.6d
    • ISIM support is not available
    • The supported operating system is 32-bit Fedora 16.2 Linux. Windows driver support is not available.
    • If design files are changed, there is a possibility that timing will not be met.
      Users may need to run MAP with different cost table values to meet timing.
      The implementation script allows the user to set a cost table value.
      Use the tag option of implement.sh to make output directories unique.
      Every effort has been made to have the default cost table meet timing, however due to varying conditions the default cost table cannot be guaranteed to meet timing.
    • Bitstream compatibility between General ES and Production devices with design tools version 14.2 / 2012.2 (Xilinx Answer 50906)
    • Speed file patch for General ES devices when using design tools 2013.1 (Xilinx Answer 55661)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Child Answer Records

Associated Answer Records

AR# 45679
Date Created 02/13/2012
Last Updated 03/26/2015
Status Active
Type Known Issues
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit