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AR# 45682

13.1 Virtex-6 PACK - ROM16X1 INIT values can be corrupted by LUT combining.

Description

My design is not working correctly and I have traced the problem to a ROM16X1 whose output is not behaving correctly. I notice in FPGA Editor that the ROM16X1 shares a LUT complex with a route-thru LUT used to access one of the FF BELs in the slice. Are there any known issues that could explain this issue?

Solution

There is a known problem where ROM16X1 LUTs are mishandled when LUT combined. The INIT values are not being modified properly to account for the shared pin used by the other LUT. This problem has been fixed for ISE 13.2 softwareby changing PACK so that ROM16X1s are no longer LUT combined and so are never corrupted. A work around for ISE sofwareversions prior to 13.2 is to use packing constraints to prevent ROM16X1s from being LUT combined. This usually involves the use of XBLNM constraints to prevent unrelated FFs from being packed into the same slice with the ROM16X1s.
AR# 45682
Date Created 01/05/2012
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • Less