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Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions

AR# 45702

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Topic PCIe
Last Updated 01/09/2012
Status Active
Description

This Release Notes and Known Issues Answer Record is for the AXI Interface version of the Spartan-6 FPGA Integrated Block for PCI Express, first released in ISE Design Suite 12.3.

Solution


For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

General Information

New Features
  • ISE 13.4 software

Supported Devices
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA LX/LXT
  • Spartan-6 XQ LX/LXT

NOTE: For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Known Issues



This table correlates the core version to the first ISE release version in which it was included.


Core Version
ISE Version
v2.4
ISE 13.4
v2.3
ISE 13.2
v2.2
ISE 12.4
v2.1
ISE 12.3

The following table provides known issues for the AXI inteface version of the Spartan-6 Integrated Block for PCI Express.

NOTE: The "Version Found" column lists the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Article Number
Article Title
Version Found
Version Resolved
(Xilinx Answer 36416)
User implemented configuration space registers starting addresses are not customizable
v2.1
Not Resolved
(Xilinx Answer 39063)
Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts?
v2.1
Not Resolved
(Xilinx Answer 42454)
CORE Generator GUI shows a value of 0 for bit 15 of the Device Capabilities Register
v2.1
Not Resolved
(Xilinx Answer 38886)
WARNING:XdmHelpers:376 - Unexpected value of "1'b0" found for attribute GTP_SEL.
v2.1
Not Resolved
(Xilinx Answer 42339)
What is the PMA_RX_CFG setting for an asynchronous link?
v2.1
Not Resolved
(Xilinx Answer 42749)
Some bits of m_axis_rx_tuser not defined in User Guide
v2.1
v2.4
(Xilinx Answer 44442)
AXI Transmit Packet is Dropped due to L0s Entry
v2.1
v2.4
(Xilinx Answer 38717)
Minimum sys_reset assertion length to properly reset the core
v2.1
v2.3
(Xilinx Answer 39548)
Replay Timeout is occurring too fast when using VHDL wrapper
v2.1
v2.3
(Xilinx Answer 40626)
DRC Error During Simulation using Provided Root Port Model
v2.1
v2.3
(Xilinx Answer 42569)
List of other issues resolved in v2.3
v2.3
v2.3
(Xilinx Answer 37955)
VHDL Wrapper Not Available for v2.1 Release
v2.1
v2.2
(Xilinx Answer 37595)
SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6"
v2.1
v2.2
(Xilinx Answer 39371)
List of other issues resolved in v2.2
v2.2
v2.2
(Xilinx Answer 37939)
List of other issues resolved in v2.1
v2.1
v2.1


Revision History

01/18/2012 - Initial release
Applies To

IP

  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
 
 
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