For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.
NOTE: For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.
This table correlates the core version to the first ISE release version in which it was included.
|User implemented configuration space registers starting addresses are not customizable|
|Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts?|
|CORE Generator GUI shows a value of 0 for bit 15 of the Device Capabilities Register|
|WARNING:XdmHelpers:376 - Unexpected value of "1'b0" found for attribute GTP_SEL.|
|What is the PMA_RX_CFG setting for an asynchronous link?|
|Some bits of m_axis_rx_tuser not defined in User Guide|
|AXI Transmit Packet is Dropped due to L0s Entry|
|Minimum sys_reset assertion length to properly reset the core|
|Replay Timeout is occurring too fast when using VHDL wrapper|
|DRC Error During Simulation using Provided Root Port Model|
|List of other issues resolved in v2.3|
|VHDL Wrapper Not Available for v2.1 Release|
|SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6"|
|List of other issues resolved in v2.2|
|List of other issues resolved in v2.1|
01/18/2012 - Initial release