New Features

• 13.4 ISE Design Suite support
• Incorporated latest ISE 13.4 Transceiver Wizard wrappers

Supported Devices

• Kintex-7 XC
• Virtex-7 XC
• Spartan-6 XQ LX/LXT
• Virtex-5 XQ LXT/FXT/SXT
• Virtex-6 XQ LXT/SXT
• Spartan-6 XC LXT
• Virtex-4 XC FX
• Virtex-5 XC LXT/FXT/SXT/TXT
• Virtex-6 XC CXT/LXT/HXT/SXT
• Virtex-6L XC LXTL/SXTL

NOTE: For a complete part and package support list, please check theXilinx CORE Generator interface (under 'Supported Families') for XAUI v10.2.

Resolved Issues

• (Xilinx Answer 42673) - LogiCORE IP XAUI v10.1, 7 Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2/13.3
• (Xilinx Answer 42850) - RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices?
• (Xilinx Answer 42842) - 7 Series GTX Transceiver - PLLREFCLK selection change causing simulation issue in ISEDesign Suite 13.1
• (Xilinx Answer 44392) - LogiCORE IP XAUI v10.1, Kintex-7/Virtex-7 - GTRXRESET pin must be asserted until the PLL has locked
• (Xilinx Answer 43482) - 7 Series GTX Transceiver Reset Requirements Upon Configuration
• (Xilinx Answer 44858)- LogiCORE IP XAUI v10.1 - GTn_RXCDRRESET and GTn_RXBUFRESET port connection changes in the block wrapper for 7 Series devices in ISE Design Suite 13.2/13.3
• CR631071
  Datapath FF reset optimization
• CR555469
  Incorrectly performs check_end functions on /T/ with inverted disparity (corner case)
• CR576615
  Testbench enhanced to poll MDIO or Status Vector to determine link-up.

Known Issues resolved in v10.2 rev1

• (Xilinx Answer 45816) - LogiCORE IP XAUI v10.2 - GUI does not correctly restrict selection of 20G data rate and non 802.3 State Machines

Known Issues in v10.2 and v10.2 rev1

• (Xilinx Answer 40897) - LogiCORE IP - Xs are seen in ModelSim 6.6c functional or timing simulation
• (Xilinx Answer 35241) -LogiCORE IP XAUI v9.2 - Timeout is seen in some Virtex-5 FPGA Example Design Timing Simulation
• (Xilinx Answer 24678) - Virtex-4 FPGA GT11 SmartModel Simulation - TX serial output skewed in SimPrims Timing Simulation
• (Xilinx Answer 45405)- LogiCORE IP XAUI v10.2 - Required changes to implement the core on 7 Series IES devices
• (Xilinx Answer 46483) - XAUI v10.2 and RXAUI v2.2 - Core fails to regain Synchronization after link partner restarts transmission on 7 Series Devices
• (Xilinx Answer 45497) - XAUI v10.1/v10.2 - sync_status is de-asserted during data transfer on Kintex-7 and Virtex-7 Initial or General ES devices
• (Xilinx Answer 46707) - XAUI v 10.2 - Required changes to implement the core on 7 Series General ES devices

Download Rev1 Update

To get the Rev1 update to resolve the issue described above, apply the following patch to the Xilinx ISE 13.4 software installation: http://www.xilinx.com/txpatches/pub/swhelp/ise13_updates/ar45705_xaui_v10_2_rev1.zip

Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE 13.4 software installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

After installing the patch, regenerate the LogiCORE IP XAUI v10.2 core in the 13.4 CORE Generator tool.For further information on finding the Xilinx installation and using environment variables, see (Xilinx Answer 11630).

NOTE: You might need system administrator privileges to install the patch if you do not have write permissions to the Xilinxinstallation directory.