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This Answer record provides solution for the following issues seen with Aurora 64B66B V6.2
X's seen on signals during timing simulation of the core
No Channel UP in timing simulation
TRACE reports timing errors
GT REFCLK period in UCF differs with GT REFCLK period of DEMO_TB because of rounding of digits. This results in signals being driven to 'X' & design does not get CHANNEL UP for data transfer.To work around this issue, use the GT REFCLK value period from UCF for CLOCKPERIOD_1 and CLOCKPERIOD_1 parameters/constants in DEMO_TB.
Make sure all the transceivers are placed continuously in multi-lane design. This helps ISE software tools meet timing easily
Check if a standard GT REFCLK value is available for required Line rate
In <USER_COMPONENT_NAME>_wrapper.v[hd] file add the following code:
always @(posedge rxrecclk_64_i) begin if(!resetdone_i) begin rx_resetdone_r1 <= `DLY 1'b0; rx_resetdone_r2 <= `DLY 1'b0; end else begin rx_resetdone_r1 <= `DLY resetdone_i; rx_resetdone_r2 <= `DLY rx_resetdone_r1; end end