"Signal m_axis_rx_tvalid never deasserts mid-packet"
This is not correct.
It is possible for them_axis_rx_tvalid signal to deassert (go Low)during the middle of a packet. Users must qualify their incoming data by ensuring m_axis_rx_tvalid is asserted each cycle.
This does not apply to the 64-bit inteface (non x8 Gen 2 applications). For the 64-bit interface, m_axis_rx_tvalid does not deassert mid-packet as stated in the User Guide.
If you have any questions related to this issue, please open a WebCasewith Xilinx Support and refer to this answer record number (45771).
02/01/2012 - Initial Release
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.