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AR# 45771 Design Advisory for the Virtex-6 Integrated Block for PCI Express - The receive interface signal m_axis_rx_tvalid might deassert in the middle of a packet when using the 128-bit x8 Gen 2 interface

Description

Version Found: v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

For x8 Gen 2 applications using the 128-bit interface,the User Guide has the following statement:

"Signal m_axis_rx_tvalid never deasserts mid-packet"

This is not correct.

Solution

It is possible for them_axis_rx_tvalid signal to deassert (go Low)during the middle of a packet. Users must qualify their incoming data by ensuring m_axis_rx_tvalid is asserted each cycle.

This does not apply to the 64-bit inteface (non x8 Gen 2 applications). For the 64-bit interface, m_axis_rx_tvalid does not deassert mid-packet as stated in the User Guide.

If you have any questions related to this issue, please open a WebCasewith Xilinx Support and refer to this answer record number (45771).

Revision History
02/01/2012 - Initial Release

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A
33775 Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33775 Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express N/A N/A

Actions

AR# 45771
Date Created 02/02/2012
Last Updated 07/06/2012
Status Active
Type Design Advisory
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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