The Kintex-7 and Virtex-7 FPGA XADC INL specification in the data sheet is +/- 3 LSBs.
The datasheet specifies the need to set a new BitGen option to achieve the best INL performance with the XADC.
This answer record provides more information on how to enable this BitGen option.
As documented in the 7 series device datasheets, to achieve the improved linearity (INL) of +/-3 LSBs, a new BitGen option must be used. The BitGen option is called XADCEnhancedLinearity and can be set to either ON or OFF (the default is OFF). Any existing designs implemented prior to the addition of this attribute will function with XADCEnhancedLinearity = OFF. The designs can be run through BitGen again to set the XADCEnhancedLinearity = ON.
To set this BitGen option in the ISE design tools, perform the following:
In Vivado, you can set the device configuration options (same as Bitgen options) by using the set_property command in an XDC file.
Example syntax. set_property BITSTREAM.GENERAL.XADCENHANCEDLINEARITY On [current_design]
Turning the XADCEnhancedLinearity ON improves the INL from a worst case of 5 LSBs to 3 LSBs, and also improves THD and SNR. However, there is an effect on the ADC transfer function that introduces clipping (~10mV) of the analog input range (1V) due to the offset and gain correction. This behavior can also occur for Virtex-6 devices when calibration is enabled. For further details, see the Calibration Example section of the Virtex-6 System Monitor User Guide (UG370).
For ES silicon, INL had originally been specified as +/-2 LSB but was subject to an Errata item. Applying the XADCEnhancedLinearity option will achieve +/- 3LSBs of INL for this silicon.
Production Silicon now features INL of +/-3LSBs, which is dependent on having the XADCEnhancedLinearity BitGen option set.