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AR# 45781 Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option

The Kintex-7 and Virtex-7 FPGA INL specification in the data sheet is2 LSBs. Please check the errata document which accompanies the devices to see if this item applies. The errata document contains an errata item specifying an INL of 3 LSB. The errata calls out the need to set a new BitGen option to achieve 3 LSBs. This answer record provides more information on how to enable this BitGen option.

As documented in the Kintex-7 FPGA Errata for XADC, to achieve the improved linearity (INL) of +/-3 LSBs, a new BitGen option must be used. The BitGen option is called XADCEnhancedLinearity and can be set to either ON or OFF (the default is OFF). Any existing designs implemented prior to the addition of this attribute will function with XADCEnhancedLinearity = OFF. The designs can be run through BitGen again to set the XADCEnhancedLinearity = ON.

To set this BitGen option in the ISE design tools, perform the following:

  1. Right-click on the Generate Programming File, select Advanced Property display level.
  2. Add -gXADCEnhancedLinearity to the "Other Bitgen Command Line Options" as shown below:


Turning the XADCEnhancedLinearity ON improves the INL from a worst case of 5 LSBs to 3 LSBs, and also improves THD and SNR. However, there is an effect on the ADC transfer function that introduces clipping (~10mV) of the analog input range (1V) due to the offset and gain correction. This behavior can also occur for Virtex-6 devices when calibration is enabled. For further details, see the Calibration Example section of the Virtex-6 System Monitor User Guide (UG370).

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42944 Design Advisory Master Answer Record for Virtex-7 FPGA N/A N/A
42946 Design Advisory Master Answer Record for Kintex-7 FPGA N/A N/A
AR# 45781
Date Created 01/12/2012
Last Updated 09/06/2012
Status Active
Type Design Advisory
Devices
  • Kintex-7
  • Virtex-7
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