As documented in the Kintex-7 FPGA Errata for XADC, to achieve the improved linearity (INL) of +/-3 LSBs, a new BitGen option must be used. The BitGen option is called XADCEnhancedLinearity and can be set to either ON or OFF (the default is OFF). Any existing designs implemented prior to the addition of this attribute will function with XADCEnhancedLinearity = OFF. The designs can be run through BitGen again to set the XADCEnhancedLinearity = ON.
To set this BitGen option in the ISE design tools, perform the following:

Turning the XADCEnhancedLinearity ON improves the INL from a worst case of 5 LSBs to 3 LSBs, and also improves THD and SNR. However, there is an effect on the ADC transfer function that introduces clipping (~10mV) of the analog input range (1V) due to the offset and gain correction. This behavior can also occur for Virtex-6 devices when calibration is enabled. For further details, see the Calibration Example section of the Virtex-6 System Monitor User Guide (UG370).
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |
| 42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |