UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45859

Design Assistant for PCI Express - How to bypass receiver detect when using the Virtex-6 Integrated Block for PCI Express

Description

Receiver detect is used by the transmitter to detect if a receiver is present at the other end of the link. The Virtex-6 Integrated Block for PCI Express and GTX Transceivers support this functionality. However, due to various reasons such as board signal integrity or issues with the link partner receiver, sometimes it is helpful to bypass the receiver detect function and allow the core to go straight to the LTSSM polling state.

NOTE:This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536).The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe.Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

During the DETECT state, the integrated block asserts PIPETXRCVRDET to instruct the GTX transceivers to perform receiver detect. This signal is renamed and called TXDetectRx in the gtx_wrapper_v6.v[hd] file. If a receiver is present on a given lane, the GTX transceiver responds by asserting 011b on RXSTATUS and asserting PHYSTATUS high for one cycle.

It is sometimes helpful to bypass the GTX response and indicate to the block that a receiver is always present. This can be done by adding the following code to the gtx_wrapper_v6.v[hd] file.

Note that doing this is technically not compliant to the PCI Express specification. However, realistically, it is unlikely to cause any problems. If a receiver is truly not present on a given lane, the block still sends TS1 training sets upon the transition to the POLLING state. However, once CONFIGURATION is entered, the block will realize the lane is not used and instruct the GTX transceiver to send electrical idle on the unused lanes.

Verilog

//Add the following
wire [(NO_OF_LANES*3)-1:0] int_RxStatus;
reg [(NO_OF_LANES*3)-1:0] reg_RxStatus;

always @*
begin
if (TxDetectRx)
reg_RxStatus <= 24'b011011011011011011011011;
else
reg_RxStatus <= int_RxStatus;
end

assign RxStatus = reg_RxStatus;

// Change the following
.USER_RX_STATUS ( RxStatus[(3*i)+2:(3*i)] ), //O
// to
.USER_RX_STATUS ( int_RxStatus[(3*i)+2:(3*i)] ), //O

VHDL

//Add the following
signal int_RxStatus : std_logic_vector(((NO_OF_LANES * 3) - 1) downto 0);
signal reg_RxStatus : std_logic_vector(((NO_OF_LANES * 3) - 1) downto 0);

process (all)
begin
if (TxDetectRx = '1') then
reg_RxStatus <= "011011011011011011011011";
else
reg_RxStatus <= int_RxStatus;
end if;

RxStatus <= reg_RxStatus;
end process;

// Change the following
USER_RX_STATUS => RxStatus_v6pcie7((3 * i) + 2 downto (3 * i)), --O
// to
USER_RX_STATUS => int_RxStatus((3 * i) + 2 downto (3 * i)), --O

Revision History:
1/17/2012 - Initial Release

AR# 45859
Date Created 01/18/2012
Last Updated 03/06/2013
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )