We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4595

Synopsys Design Compiler: How to specify the INIT attribute on instantiated ROM/RAM primitives


Keywords: Synopsys, Design Compiler, INIT, ROM16X1, ROM32X1,
set_attribute, attribute

Urgency: Standard

General Description:

This Solution record describes how to specify the INIT attribute on
instantiated ROM/RAM primitives in a Synopsys Design Compiler
Verilog or VHDL design. The INIT attribute specifies the
initialized value of the component and is required on the ROM
primitives (ROM16X1, ROM32X1) if instantiated in the design.


Before specifying the set_attribute command to initialize the
ROM/RAM components, the following line needs to be added to the
.synopsys_dc.setup file if it is not already there:

edifout_write_properties_list = {"instance_number" "pad_location" "part" "INIT"}

In order the specify the INIT attribute, the following line may be
placed into the Synopsys compile script before writing out the
SEDIF netlist:

set_attribute "<instance_name>" "INIT" -type string "<value>"

where <instance_name> is replaced by the instance name given to the
instantiated ROM/RAM primitive and <value> is the hex value desired
to be placed on that component.

Repeat this command for each ROM/RAM component you wish to
AR# 4595
Date Created 08/31/2007
Last Updated 10/01/2008
Status Archive
Type General Article