UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45953

7 Series - On chip termination for High Range banks

Description

The 7 Series High Range (HR) banks do not support DCI. Is there an On Chip termination that can be used on HR banks?

Solution

The 7 Series HR banks (General ES and onwards) support uncalibrated input termination for certain I/O Standards that can reduce the need for external resistors. This is similar to the Spartan-6 FPGA internal input termination documented in UG381, the Spartan-6 SelectIO User Guide. The structure is that of a pull-up and pull-down resistor in parallel, providing a Thevenin-equivalent termination resistance to a VCCO/2 level. The IN_TERM attribute can be set to NONE (default), UNTUNED_SPLIT_40, UNTUNED_SPLIT_50, or UNTUNED_SPLIT_60. IN_TERM is supported on all the SSTL and HSTL I/O Standards.
AR# 45953
Date Created 01/20/2012
Last Updated 02/09/2012
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT