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AR# 45988 AXI Bridge for PCI Express - 1 DW Write Transactions on the AXI4 Slave interface create malformed TLPs when using a 32-bit AXI data width

Description

Version Found: 1.00.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

Any 1DW or less AXI Write Transaction on the Slave interface of the AXI Bridge for PCI Express will result in a malformed TLP upstream when the AXI data width is 32-bit. Currently, the 32-bit interface is only used for Spartan-6 FPGA designs. Therefore, this issue is not present in Virtex-6 or 7 Series devices.

NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

Solution

To resolve this issue, follow these instructions:

  1. Make the IP local; to make the IP local:
    1. Find the IP in the System Assembly view and right-click the IP.
    2. Select Make This IP Local.
  2. After the IP is local, go to the "<xps project directory>/pcores/axi_pcie_v1_02_a_axi_pcie_mm_s_v1_02_a/hdl/vhdl" directory.
  3. Open the axi_slave_write.vhd file in a text editor.
  4. Go to line 703 of this file. The following line should be found:

    first_BE <= strobe_pipe(0)(beat_count*4-1 downto beat_count*4-4);
  5. Replace line 703 with the following 5 lines:

    if length_bytes_int < 5 then
     last_BE <= (others => '0');
    else
     last_BE <= strobe_pipe(0)(beat_count*4-1 downto beat_count*4-4);
    end if;

Revision History
01/26/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
46624 AXI Bridge for PCI Express - Using Root Port configuration a packet that does not actually target the BAR can be passed to the AXI Memory Mapped Bridge N/A N/A
46623 AXI Bridge for PCI Express - Using 128-bit Interface (x8 Gen 1 or x4 Gen 2), an array size mismatch occurrs on Completions with Data with status of Completor Abort or Unsupported Request N/A N/A
46622 AXI Bridge for PCI Express - Large read request from AXI may cause completion timeout if link partner not releasing non-posted credits fast enough N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions N/A N/A

Actions

AR# 45988
Date Created 01/26/2012
Last Updated 07/01/2012
Status Active
Type Known Issues
Devices
  • Spartan-6 LXT
IP
  • AXI PCI Express (PCIe)
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