We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
Any 1DW or less AXI Write Transaction on the Slave interface of the AXI Bridge for PCI Express will result in a malformed TLP upstream when the AXI data width is 32-bit. Currently, the 32-bit interface is only used for Spartan-6 FPGA designs. Therefore, this issue is not present in Virtex-6 or 7 Series devices.
NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.
To resolve this issue, follow these instructions:
Make the IP local; to make the IP local:
Find the IP in the System Assembly view and right-click the IP.
Select Make This IP Local.
After the IP is local, go to the "<xps project directory>/pcores/axi_pcie_v1_02_a_axi_pcie_mm_s_v1_02_a/hdl/vhdl" directory.
Open the axi_slave_write.vhd file in a text editor.
Go to line 703 of this file. The following line should be found: