We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46020

MIG 7 Series v1.1-v1.4 QDRII+ - Why is the QVLD signal left unconnected?


The MIG 7 Series v1.1-v1.4 QDRII+ design never uses the QVLD signal and leaves it unconnected. 


This signal can be commented out in the UCF file to prevent any implementation errors, and can be safely removed from the design.

If the signal is not removed, the following warning occurs during BitGen:

WARNING:PhysDesignRules:367 - The signal <qdriip_qvld<0>_IBUF> is incomplete. The signal does not drive any load pins in
the design.

The QVLD signal is removed from the MIG QDRII+ design in the 14.1 software release.

AR# 46020
Date Created 01/26/2012
Last Updated 08/13/2014
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • MIG 7 Series