Solution

RTL Changes:

1. Open the "user_design/rtl/phy/ddr_phy_init.v" module and uncomment the following lines:
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];

NOTE: Starting in MIG v1.5, available with ISE 14.1, this step can be skipped. Go directly to Step 2.

2. Modify the following top level parameters in the "example_design/rtl/example_design.v" and "user_design/rtl/core_name.v" modules:

RTT_NOM = "DISABLED"
RTT_WR = "60"
USE_ODT_PORT = "0"

As per the Jedec standard, Dynamic ODT cannot be used during Write Leveling. For this reason, the 7 Series MIG PHY turns Dynamic ODT off and sets RTT_NOM to 40 ohm before Write Leveling. After Write Leveling completes, the MR1 and MR2 mode registers are reprogrammed with the Dynamic ODT settings (RTT_NOM=Disabled and RTT_WR=60). When running a simulation, you will see Dynamic ODT disabled settings during initialization, but then a second set of MR1/MR2 commands sent after Write Leveling completes showing the appropriate Dynamic ODT settings as follows:

sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1 DLL Enable = Enabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1 Additive Latency = 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1 Write Levelization = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 11980948.0 ps INFO: Load Mode 1 Qoff = Enabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 13280948.0 ps INFO: Load Mode 2
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 13280948.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 13280948.0 ps INFO: Load Mode 2 CAS Write Latency = 5
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 13280948.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 13280948.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 13280948.0 ps INFO: Load Mode 2 Dynamic ODT Rtt = 60 Ohm

NOTE: Usage of this special ODT use case is available to users that have placed ODT on a site that violates the rules in (Xilinx Answer 45633).