UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4611

VCS - Time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF

Description

Keyword: Verilog, acchold, X_RAM

Urgency: Standard

General description:
When performing simulation using "time_sim.v" generated by
NGD2VER, VCS gives the following errors :
time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF

Solution

The errors/warnings are due to the TIMINGCHECK properties in
the SDF file not matching the timing checks specified in SIMPRIM
Verilog models. The SDF file is specified for both posedge and
negedge, but the SIMPRIMS only specify posedge.

A1.5i contains the patched version of the Verilog SIMPRIM models
that include timing checks for both posedge and negedge edges
instead of just one check without any edge qualifier.

This is fixed for A2.1i.
AR# 4611
Date Created 08/31/2007
Last Updated 03/08/2001
Status Archive
Type ??????