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AR# 4611

VCS - Time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF


Keyword: Verilog, acchold, X_RAM

Urgency: Standard

General description:
When performing simulation using "time_sim.v" generated by
NGD2VER, VCS gives the following errors :
time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF


The errors/warnings are due to the TIMINGCHECK properties in
the SDF file not matching the timing checks specified in SIMPRIM
Verilog models. The SDF file is specified for both posedge and
negedge, but the SIMPRIMS only specify posedge.

A1.5i contains the patched version of the Verilog SIMPRIM models
that include timing checks for both posedge and negedge edges
instead of just one check without any edge qualifier.

This is fixed for A2.1i.
AR# 4611
Date 03/08/2001
Status Archive
Type ??????
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