The MIG 7 Series DDR3/DDR3 designs require specific trace matching guidelines be followed to ensure the target data rate be achieved. These trace matching guidelines are specified in the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide.
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The trace matching requirements specified in the user guide are between:
The user guide specifies not only the matching requirements for maximum operation, but how much the guidelines can be loosened for slower interfaces. Refer to the user guide for specific trace matching numbers.
In general, trace lengths should be kept to less than 3 inches.
Additional Information
(Xilinx Answer 51296) Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases
(Xilinx Answer 42024) 7 Series MIG DDR3 - What is the recommended trace impedance between the FPGA and the DDR3 SDRAM?
Revision History
08/24/12 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51475 | MIG 7 Series Design Assistant - MIG 7 Series DDR2/DDR3, Board Layout and Design Guidelines | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51296 | Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases | N/A | N/A |
| 42024 | MIG 7 Series DDR3 - What is the recommended trace impedance between the FPGA and the DDR3 SDRAM? | N/A | N/A |