In all Spartan-6 devices, the PLL_BASE and PLL_ADVwith a non-zero CLKOUT3_PHASE attribute can generate an incorrect phase shift on the CLKOUT3 output. This is caused bya software issue resultingin an incorrect setting of the PLL configuration bits. A full analysisverified that no other outputs areimpacted.
To determine if a design is not impacted, FPGA Editor can be opened with the design's .ncd file. Open each PLL block,select the 'Show/Hide Attributes' button ('F=') on the top menu bar, andcheck the value of CLKOUT3_PHASE to verify that it is zero.
In designs that are impacted,a typicalsetup with CLKOUT3_DIVIDE values of 8 or less, the phase shift error has been seen to be 45 degrees or more, which should make the error evident in hardware. However, the degree of phase shift error varies depending on PLL and PHASE settings, so it is best to check the design in hardware testing for verification.Software timing analysis and simulation will not reflect the error since it occurs in BitGen.
This issue affects all previous and current versions of software, including ISE 13.4. A fixwill beimplemented inthe next ISE software release.
The primary workaround is to avoid the CLKOUT3 output for any clocks that are being phase shifted. The CLKOUT3 output can be used with the default phase shift of 0.
For additional assistance or for designs that cannot use the recommended workaround, please contact Xilinx Technical Support at www.support.xilinx.com