The following answer records cover current known issues as well as commonly asked questions related to MIG 7 series.
NOTE: This answer record is part of the Xilinx MIG 7 Series Solution Center (Xilinx Answer 34243). The Xilinx MIG 7 Series Solution Center is available to address all questions related to MIG 7 series. Whether you are starting a new design with MIG 7 series or troubleshooting a problem, use the MIG 7 Series Solution Center to guide you to the right information.
MIG Known Issues
(Xilinx Answer 45195) MIG 7 Series - Release Notes and Known Issues for All Versions
MIG Design Advisories
(Xilinx Answer 33566) Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
MIG 7 Series Top Issues
(Xilinx Answer 50461) MIG 7 Series - Calibration updates in MIG 7 Series v1.6 available with ISE Design Suite 14.2
(Xilinx Answer 47043) MIG 7 Series DDR3/DDR2 - Addition of MMCM to clocking structure starting with v1.5 (available with ISE Design Suite 14.1)
(Xilinx Answer 43344) MIG 7 Series DDR3 - Is Dynamic Calibration supported for DDR3 designs (updated with 14.1 MIG toolrelease)?
(Xilinx Answer 43879) 7 Series MIG DDR3 - Hardware Debug Guide
(Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified
(Xilinx Answer 40603) MIG 7 Series DDR3/DDR2 - Clocking Guidelines
(Xilinx Answer 41752) MIG 7 Series DDR3/DDR2 - Can an x16 interface fit into a single bank?
(Xilinx Answer 42036) MIG 7 Series- Internal/External Vref Guidelines
(Xilinx Answer 42665) MIG 7 Series - Why does the MIG Example Design fail in BitGen?
Initial ES and General ES Information
(Xilinx Answer 43347) Kintex-7 FPGA Initial Engineering Sample (ES) Master Answer Record and Known Issues
(Xilinx Answer 45696) Kintex-7 FPGA General Engineering Sample (ES) Master Answer Record and Known Issues
(Xilinx Answer 43423) Virtex-7 FPGAInitial Engineering Sample (ES) Known Issues Master Answer Record
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51287 | Xilinx MIG Solution Center - Top Issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45195 | MIG 7 Series - Release Notes and Known Issues for All Versions | N/A | N/A |
| 33566 | Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores | N/A | N/A |
| 43879 | 7 Series MIG DDR3/DDR2 - Hardware Debug Guide | N/A | N/A |
| 45633 | Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified | N/A | N/A |
| 40603 | MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines | N/A | N/A |
| 41752 | MIG 7 Series DDR3/DDR2 - Can a x16 interface fit into a single bank? | N/A | N/A |
| 42036 | MIG 7 Series - Internal/External VREF Guidelines | N/A | N/A |
| 42665 | MIG 7 Series - Why does the MIG Example Design fail in BitGen? | N/A | N/A |