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AR# 46231

13.4 EDK - How to instantiate a System Generator PCORE in XPS

Description

I have a System Generator model, which uses a black box to incorporate a top-level VHDL file. I keep getting errors similar to below:

ERROR:NgdBuild:604 - logical block
'transmitter_axiw_0/transmitter_axiw_0/sysgen_dut/transmitter_x0/black_box/DD
S_inst' with type 'DDS' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, case mismatch between the block name
and the edif or ngc file name, or the misspelling of a type name. Symbol
'DDS' is not supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block
'transmitter_axiw_0/transmitter_axiw_0/sysgen_dut/transmitter_x0/black_box/PL
L_307_2MHz_MMCM' with type 'MMCM_PLL_307MHz' could not be resolved. A pin
name misspelling can cause this, a missing edif or ngc file, case mismatch
between the block name and the edif or ngc file name, or the misspelling of a
type name. Symbol 'MMCM_PLL_307MHz' is not supported in target 'virtex6'.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1

Solution

When exporting from System Generator as a PCORE,so long asthe _config.m file is set up correctly thePCORE directory structure should becorrect and all the files should be there.

In the _config.m, specify the .ngc filesfor the cores that are inthe blackbox portion of the design. The syntax for this is:


this_block.addFile('corename.ngc');


Add this type of line for every file that is referenced by the blackboxtop level.This is similar to a compile order for a BBD file and System Generator will annotate the BBD file correctly.

AR# 46231
Date Created 03/05/2012
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • EDK - 13.4