UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46233

LogiCORE IP Video Deinterlacer v1.0 - When performing VFBC writes, why do I see a mismatch between documentation and the example test bench?

Description

When performing VFBC writes, why do I see a mismatch between documentation and the example test bench?

Solution

There is atypo in the document that can cause some confusion whichis going to becorrected in the next release.

The burst length is1024, but this is in bytes (not words).So, bursting is actually being performed at 256*32-bit words, whilethe documentationindicates 128. The burst size was increased from 128 to 256 to help with real world MPMC performance issues, but the documentation was not properly updated to reflect this change.

Also, Figure 1 below is a screenshot of a full burst simulation followed by the start of the second burst.Theremight be some confusion because the command bus does not align with the start of the data burst.The next command is queued into the VFBC early, that is, before the last data burst ends.

Figure 1: Video Deinterlacer VFBC Write Command
Figure 1: Video Deinterlacer VFBC Write Command

Figure 1: Video Deinterlacer VFBC Write Command

For a detailed list of LogiCORE IP Video Deinterlacer Release Notes and Known Issues, see (Xilinx Answer 41969).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
41969 LogiCORE IP Video Deinterlacer - Release Notes and Known Issues N/A N/A
AR# 46233
Date Created 02/09/2012
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Video Deinterlacer