How much capacity does the SEM Controller require for a storage device targeting an XC7VX1140T device?
How is the SEM controller implemented in XC7VX1140T?
For an SSI device, does it need multiple SEM cores?
For error classification only, it would require a 512Mbit SPI Flash.
For classification and replace it would require a 1024Mbit SPI Flash.
Child SEM is implemented in each SLR, and these controllers are merged as one controller.
For details, please check an example design. You can create this by generating an SEM IP for SSI devices.