The rxsync signal represents the synchronization request(sync~) signal from the specification. The 4-bits of the SYNC~ signal give us byte resolution (it is a 32-bit datapath). These signals could be ORedtogether to produce a 1-bit SYNC~ signal.
In JESD204A and JESD204B subclass0 and 2 devices, SYNC~ will go High when all lanes have received valid K28.5s so that their code group synchronization state machines are out of state CS_ININ (section 7.1 in the JESD204 specification).
For JESD204B subclass 1 devices, it will go High on the first local multiframe clock(LMFC) crossing after a SYSREF pulse is received at the FPGA, providing valid K28.5s are received as before (section 6.3 of the specification has more details on this topic).
ForLogiCORE IP JESD204Release Notes from other versions, see(Xilinx Answer 44405).