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AR# 4629

FPGA Express - "Error: Clock variable 'xxx' is being used as data (HDL-175)."


Keywords: clock, data, Express, HDL-175

Urgency: Standard

General Description:
When I synthesize a design using FPGA Express v2.x, the following error occurs:

"Error: Clock variable 'CLK' is being used as data . (HDL-175)"



This error will occur if the signal ("CLK", in this case) is used as both a clock signal and as regular data.

In most cases, this issue has been resolved FPGA Express in versions 3.0 and newer. However, some issues of this type still exist and will be fixed in a future release of FPGA Express.


To work around this issue, change the source code so that the signal in question is not being used as both a clock and as data.

A simple way to do this is to assign the signal to an intermediate variable and use that intermediate value as the "data", while using the original signal as the "clock". In most cases, FPGA Express will optimize the intermediate signal out of the design so that there are no timing or resource utilization penalties.
AR# 4629
Date Created 09/17/1998
Last Updated 08/11/2003
Status Archive
Type General Article