We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46311

System Generator - Avoid naming MDL files after Xilinx blockset elements


Naming the System Generator MDL files similar or the same as Xilinx blockset elements can cause irregular errors from System Generator.

For example, an EDK Processor block and a Shared Memory block contained in a single MDL file will produce a FATAL_ERROR if the MDL is called "shared_memory.mdl". Naming it "shared_memory_1.mdl" did not cause the FATAL_ERROR.


Please avoid naming the MDL files similar to the Xilinx blockset components.
AR# 46311
Date Created 08/02/2012
Last Updated 08/03/2012
Status Active
Type General Article
  • System Generator for DSP - 13.1
  • System Generator for DSP - 13.2
  • System Generator for DSP - 13.3
  • More
  • System Generator for DSP - 13.4
  • System Generator for DSP - 13
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • ??????
  • Less