Does the port width of my C code get optimized? How about the variables that are declared? Should I be concerned about mismatching assignments of RTL signal width warnings from RTL Synthesis tool?
Top level port widthwill not be altered. Therefore, the correct sized type must be used.
The bit width of internal port between modulesmay be optimized.
It is possible that the RTL output may have a wider signal assigned to by a narrower signal. However, these warning can be safely ignored.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47431 | Xilinx Vivado HLS Solution Center - Design Assistant | N/A | N/A |