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AR# 46358

Vivado HLS - RTL Port and signal width implementation.


Does the port width of my C code get optimized? How about the variables that are declared? Should I be concerned about mismatching assignments of RTL signal width warnings from RTL Synthesis tool?


Top level port widthwill not be altered. Therefore, the correct sized type must be used.

The bit width of internal port between modulesmay be optimized.

It is possible that the RTL output may have a wider signal assigned to by a narrower signal. However, these warning can be safely ignored.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 46358
Date Created 02/15/2012
Last Updated 07/27/2012
Status Active
Type Solution Center
  • AutoESL - 2010.b
  • AutoESL - 2011.1
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  • AutoESL - 2011.4
  • Vivado - 2012.2
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