Inserting ChipScope cores in the PlanAhead tool generates unconnected ports in the 13.3 and 13.4 design tools. BitGen displays DRC errors similar to the following when this occurs:
"ERROR:PhysDesignRules:10 - The network <xxxx_cs_ila_0_0> is completely unrouted."
Solution
To avoid this issue, add KEEP attributes to the nets reported in the BitGen DRC, and run again through XST and implementation.