If using Verilog add the following to example_design/core_name_block.v:
localparam SYNC_COUNT_LENGTH = 16;
reg [SYNC_COUNT_LENGTH - 1:0] sync_counter = {SYNC_COUNT_LENGTH{1'b0}};
// Sync counter - GT requires a reset if the far end powers down
always @(posedge clk156) begin
if (sync_counter[SYNC_COUNT_LENGTH - 1]) begin
sync_counter <= {SYNC_COUNT_LENGTH{1'b0}};
end
else if (!(&sync_status_i)) begin
sync_counter <= sync_counter + 1'b1;
end
else begin
sync_counter <= {SYNC_COUNT_LENGTH{1'b0}};
end
end
// Modify the line below - add topmost bit of sync_counter into the mgt_rx_reset in your design
assign mgt_rx_reset = (... || sync_counter[SYNC_COUNT_LENGTH-1]) && reset_counter[5];
If using VHDL add the following to example_design/core_name_block.v: :
constant SYNC_COUNT_LENGTH : integer := 16;
signal sync_counter : unsigned(SYNC_COUNT_LENGTH - 1 downto 0) := (others => '0');
-- Sync counter GT requires a reset if the far end powers down.
process (clk156) begin
if rising_edge(clk156) then
if (sync_counter(SYNC_COUNT_LENGTH - 1) = '1') then
sync_counter <= (others => '0');
elsif (sync_status_i /= "1111") then
sync_counter <= sync_counter + 1;
else
sync_counter <= (others => '0');
end if;
end if;
end process;
-- Modify the line below - add topmost bit of sync_counter into the mgt_rx_reset in your design
mgt_rx_reset <= (... or sync_counter(SYNC_COUNT_LENGTH - 1)) and reset_counter(5);