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AR# 46487 MIG 7 Series v1.4 DDR3 - 2:1 mode disabled for frequencies below 400 MHz

Description

MIG 7 Series v1.4 only allows the "PHY to Controller Clock Ration" option to be set to 2:1 when the frequency range is set between the following (which corresponds to the device speed grade):

-1 400 MHz
-2 400-533 MHz
-3 400-533 MHz

This is incorrect. The user should be allowed to select 2:1 mode for frequencies less than 400 MHz.

Solution

This will be fixed in ISE 14.1 software, but users can work around this issue bymanually setting top-level parameter "nCK_PER_CLK," as long they adhere to the frequency restrictions above.

Workaround:

Generate the design you need in 4:1 mode. Then, open up the top-level example_top.v or <user_design>.v and change the following parameter:

CK_PER_CLK = 2, //This changes the memory controller clock to DRAM clock ratio from 4 to 2

Actions

AR# 46487
Date Created 02/27/2012
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-7
IP
  • MIG 7 Series
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