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AR# 46493

7 Series FPGA Design Assistant - Designing clocking structures in 7 series FPGAs


The7 series clocking structure is made up of CMT tiles; each containing one Mixed Mode Clock Manager (MMCM), onePLL, andone phaser block. In order to route clocks throughout the device,different buffer types are available. Clocks must be brought into the device using Clock-Capable Inputs. This answer record contains information on designing clocking structures for7 series FPGAs.

NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.



The Mixed Mode Clock Manager (MMCM), available in the7 series device family, allows you to perform the following:

  • Powerdown mode
  • Frequency Synthesis
  • Input Clock Switching
  • Fractional Divide
  • Dynamic Phase Shifting


The PLL in the 7 series device family has many of the same features as the MMCM, but has the following differences:

  • Higher minimum and maximumVCO frequency ranges
  • No Fractional Divide
  • No Dynamic Phase Shifting
  • 6 output clocks (O0 to O5) for the PLLinstead of 7 (O0 to O6)for the MMCM
  • No Complement outputs forfour of the output clocks


The phaser block in the CMT tile is used with memory interfaces. This block is only supported using the memory interface generator (MIG) tool. For more information on MIG, see the MIG Solution Center (Xilinx Answer 34243).

Using the Clocking Wizard

When using the MMCM or PLLin your design, Xilinx recommends that you use the Clocking Wizard, available in the CORE Generator software, to help you generate your MMCM/PLL based on your needs using an easy to use Wizard. For more information about this Wizard, including how to access the Clocking Wizard, see (Xilinx Answer 46504).

Clock Buffers

If you want to setup clock regions or control clock usage with an enable or select signal, there are a variousoptions for buffers that you can use inside your device. For additional information on the types of buffers available in the7 seriesdevice family, refer to (Xilinx Answer 46505).

Clock-Capable Inputs

External user clocks must be brought into the FPGA on differential clock pin pairs called clock-capable inputs in order to guarantee timing of the various clocking structures described above. For more information and pin placement rules, see the section called 'Clock-Capable Inputs' in the 7 Series FPGAs Clocking Resources Users Guide (UG472):http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Clocking Connectivity

For a complete list of clocking connectivity rules and restrictions, see the 'Summary of Clock Connectivity' section in the 7 Series FPGAs Clocking Resources Users Guide (UG472): http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
46370 Xilinx 7 Series FPGA Solution Center N/A N/A

Associated Answer Records

AR# 46493
Date Created 03/20/2012
Last Updated 05/20/2012
Status Active
Type 14;#
  • Artix-7
  • Kintex-7
  • Virtex-7