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AR# 46505

7 Series FPGA Design Assistant - Details on using different clocking buffers

Description

The different clock buffers available in the7 seriesdevice family allow you to setup clock regions or control clock usage with an enable or select. This answer record contains information on where to find the documentation for each of the different clock buffers available in the 7 series device family.

NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.

Solution

The following buffers are available for use with your clocks in 7 seriesFPGA designs:
  • BUFIO
  • BUFR
  • BUFMR
  • BUFG/BUFGCTRL/BUFGMUX
  • BUFH

BUFIO and BUFR

The BUFIO and BUFR buffers are used for regional clocks that do not need to reach all regions of the device. They are typically used for clocking IOSERDES interfaces. If youwant additional information on how to use either of these two buffers, you can find this information in the Regional Clocking Resources section of the7 Series FPGAsClocking Resources Users Guide (UG472): http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

BUFMR

The BUFMR is new for the 7 series device family. The BUFR and BUFIO in the 7 series device family can only route locally within its own clock region. The BUFMR must be used to route to adjacent clocking regions.The BUFMR can only be driven using the MRCC (multi-region clock capable) pins.If you want additional information on how to use this buffer, see the Multi-Region Clock Buffer section and Appendix Aof the 7 Series FPGAs Clocking Resources Users Guide (UG472): http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

BUFG, BUFGCTRL, and BUFGMUX

The BUFG, BUFGCTRL, and BUFGMUX are used for global clocks that need to reach logic throughout the entire device. You can only reach the BUFG buffers through CCIO (Clock Capable IO) pins. If youwant more information regarding how to use the BUFG buffers,see the Global Clocking Resources section of the 7 Series FPGAsClocking Resources Users Guide (UG472): http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

BUFH

The horizontal clock buffer (BUFH) drives a horizontal global clock tree spine in a single region. These buffers include a clock enable that can be used to dynamically turn the clock network on or off. This allows you to conserve power by giving you the ability to turn off regions of logic that are not in use. For more information on how to use the BUFH buffer, see the Regional Clocking Resources section of the7 Series FPGAs Clocking Resources Users Guide (UG472): http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Linked Answer Records

Associated Answer Records

AR# 46505
Date Created 03/20/2012
Last Updated 03/01/2013
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7